Experts in Vision Edge AI Implementation
About Us
ComputEra develops and productizes FPGA-based hardware accelerators for the massive workloads encountered in AI, with a focus on computer vision applications. Our proven accelerator solutions optimize FPGA chip performance and power consumption for clients with sensitive development and unit cost objectives.
ComputEra has successfully developed and deployed several accelerators for such applications as:
Object Classification
Recognizing the central object present in an image
Object Detection
Recognizing multiple objects and their bounding boxes present in the same image
Pixel Segmentation
Dividing image pixels into categories, such as buildings, trees, sky, roads, etc...
Our accelerators have been deployed on boards from multiple FPGA vendors and tested in real-life scenarios.
What We Do
ComputEra’s accelerator performs a multi-step process:
Neural Network
Training neural networks to solve AI tasks on the target dataset
Quantification
Converting the network data from floating-point to fixed-point representation
Compilation
Compiling the data into accelerator instructions streamed into the FPGA during the computation
Output
Converting the results into user-friendly output (such as bounding boxes or control sequences)
Services
Design and Planning
We help our clients navigate the accelerator design space exploration process, which involves studying the tradeoffs between performance, power, unit cost, and time-to-market. We have seen a wide variety of needs among our clients, and we have been able to leverage our expertise to find an ideal solution for each customer.
Implementation
ComputEra provides implementation (hardware IP) of all the components of the accelerator flow and supports the users in a flexible manner, and we are able to work with clients with varying levels of experience in training neural networks.
Maintenance and Evolution
ComputEra maintains a library of automated tools for our customers to adapt and customize the accelerator for speed, power consumption and accuracy. The toolbox also enables our clients to retrain the neural network to new datasets or new object classes within the same datasets.
Case Studies
Object Detection
Object Detection is perhaps the most practical use-case for Edge AI. Object Detection consists of identifying objects found in the image (or in the video stream computed by a webcam). Each objects is characterized by several parameters computed by the accelerator in real time:
- Class number (the number of classes is flexible; our demo uses 80 classes)
- Probability (indicating how likely the object is recognized correctly)
- Bounding box (showing exactly where in the image the given object is located)
The demo shown here is based on YoloNano CNN developed at University of Waterloo trained on COCO dataset using Darknet ML Framework with image size 320x320. Our accelerator is configured to run on Avnet Ultra96V2 board with Xilinx Zynq UltraScale+ MPSoC ZU3EG. Two cameras capturing images at the rate of 30 FPS (frames per second) are used in the demo. The cameras utilize only about 30% of the performance of the accelerator, which can process 200 FPS at 214MHz with power consumption close to 5W.
Object Classification
Object Classification is a simplified form of Object Detection. Object Detection finds the dominant object in the image without returning its bounding box. (It is assumed that the object plays a central role in the image and its location does not have to be returned). The CNN used for acceleration in this demo, is Darknet Tiny trained on ImageNet using Darknet ML Framework. This CNN detects 1000 classes of 224x224 pixel images. The quality is close to that of Resnet50. The ComputEra accelerator processes 75 FPS @ 200MHz with power consumption close to 3W on Efinix T120 FPGA.
Cell Mitosis Detection
Cell Mitosis Detector is yet another practical demo of the ComputEra hardware accelerator. The neural network used in Cell Mitosis Detector is a custom version of Resnet50 adapted to solve the mitosis classification problem using the publicly available dataset for this task: https://mitos-atypia-14.grand-challenge.org
The quality is sufficient to enable the use of Edge AI in an electronic microscope, which captures images of a biological tissue, partitions them into 64x64 slices, and uses the ComputEra accelerator to check for abnormal tissue formations in each slice. The accelerator performs 10,000 FPS @ 200 MHz when deployed on Avnet Ultra96V2 board with Xilinx Zynq UltraScale+ MPSoC ZU3EG.
Our Team
Sherman Liu, CEO and co-founder
- 30+ years in high tech on a variety of projects and researches related to FPGA software, architecture, EDA and AI.
- Director, FPGA Group at Cloudchip Inc, exploring FPGA-based Edge AI tool flow, including quantizer, compiler, and accelerator for CNNs.
- Director, FPGA Product at Agate Logic Inc, started and managed FPGA team including S/W tool chains, FPGA/ARM SOC firmware and SDK, architecture design and validation.
- EDA working experience with Synopsys, Cadence, Mentor Graphics.
- AI research experience in symbolic computation Prolog machine, Advanced Computer Architecture Laboratory, University of Southern California.
- B.S. in Electrical Engineering at National Taiwan University
- Ph.D. in Electrical Engineering at University of Southern California
Edwin Chu, COO
- Over 30 years of senior management experience in the semiconductor industry with a strong experience in design and operations.
- Held various leadership positions including integrated circuit design engineering, product engineering, manufacturing, and overall operations during his career.
- Vice President of Operation & AI Engineering at Cloudchip, a FPGA SoC design company.
- Management positions at National Semiconductor, Motorola and ESS Technology
- Co-founded ViewPoint Technology which was later acquired by Oak Technology and G-Design Technology later acquired by AVID Electronics.
- Master’s Degree from San Jose State University and National Chiao Tung University, Taiwan
- Awarded four U.S. patents.
Alan Mishchenko, Architect
- Researcher, UC Berkeley, https://people.eecs.berkeley.edu/~alanmi/
- Ph.D. in Computer Science, 20+ years in R&D, 200+ publications
- Known for his work in logic synthesis and formal verification, and as the main developer of open-source CAD tool ABC
- Part of the Berkeley team winning Hardware Model Checking Competition (HWMCC) in 2008-2017
- Technical interests include logic synthesis and verification, hardware design, machine learning, FPGA-based acceleration, compilation, and quantization